RISC-V is in the news. It's taking over and its great. It's going to rule the future. There's really something to this Open Source model, huh? Maybe others should try it... well, they are!

Introducing the J-Core project; an open source revision of the SH2 Instruction Set Architecture. The project may not have as much international attention as RISC-V, but that is largely due its goals being drastically different. Despite the smaller, niche market for J-Core – almost exclusively implemented on high performance FPGA's – it remains a resounding success. Not only does J-Core meet its design goals, it surpasses them, while earning the company that created it non-trivial earnings year after year.

We'll spend a little time exploring this Open Source ISA and its applications and possibilities.

What is the J-Core Open Processor?

What exactly is the J-Core Open Processor? Their website tells us quite succinctly in the opening paragraph:

J-core is a clean-room open source processor and SOC design using the SuperH instruction set, implemented in VHDL and available royalty and patent free under a BSD license.

In 2015, an engineer named Jeff Dionne, whose name may be familiar to many readers, created a new instruction set compatible with the Hitachi SuperH architecture. The patents on this ISA architecture had been allowed to expire, and that allowed this release to be licensed under the BSD license; a famously open source option.

This forms the foundation of J-Core today, which is implemented on FPGA in VHDL. While there are no integrated circuits available for this architecture today, there is nothing stopping any of us from producing such chips.

The architecture is, today, used in extremely high performance and real time compute applications. Such applications as electrical grid controllers and other critical infrastructure. Many of these applications require FPGA implementations in order to create custom circuits capable of handling these real-time workloads. This makes J-Core uniquely suited to many high-dollar markets, where organizations need highly capable FPGA implementations to handle critical compute loads.

Where J-Core Might Go

J-Core is just getting started. Today, if you want to tinker with it, you will need to purchase a targeted FPGA development board. The most affordable recommendation is the Numato Mimas v2. At $92 USD, this is out of reach for many tinkerers, especially during schooling ages. Though it is still considered quite affordable for such a capable FPGA, it is also becoming harder to find.

With the right tools and expertise, however, the platform could be ported to more devices, such as the ecp5, for which there exists an open toolchain. It's also likely compatible with various Xilinx boards, which are typically higher cost but also highly available.

These are early days for J-Core, and we can foresee a very near future where the platform begins to see photolithographically fabricated integrated circuits, or traditional chips. The SuperH Architecture is well known and beloved for its use in various famous gaming consoles and graphing calculators. This classic, powerful, and capable design deserves a chance to live in a widely available, open source ecosystem of tools.

We plan, here, to explore J-Core on various FPGAs as we learn to fabricate silicon at scale. One day, magesguild hopes to produce many IC's of various design, including J-Core chips for the open source community!

Stay tuned!

J-Core, the Other Open Source ISA

MagesGuild by Magus Gaius Mycelius, Jocundus is licensed under CC BY 4.0